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Squall Leonhart

C state tech disabled negatively affects Memory bandwidth tests

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Please post a screen shot of the Cache & Memory Benchmark Panel at both settings.

If it's possible, please run the Cache & Memory Benchmark 3 times, to see how stable the results are.

BTW, Sandra only measures memory copy bandwidth, so the value you could compare in AIDA64 is the Memory Copy benchmark. And the Memory Copy seems to be the least affected by the C-State setting.

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im trying to get a friend to replicate my findings, but so far the benchmark cache and memory tool doesn't seem to be affected by it, its only the benchmark module in the aida categories list. Arctucas reproduced otherwise, and my own testing follows his findings (note to self, don't report bugs after a 3 day stint of gaming)

It was actually brought to my attention by a post @ http://www.xtremesystems.org/forums/showpost.php?p=4024584&postcount=8

Im not sure whether to conclude this as a bug in AIDA or a side effect of not being able to shut off cores bouncing the benchmark thread about.

but yeah, i've sat there hitting refresh trying to get more than 16xxx once and the most i got was close to 17k, this change is a consistent 19xxx.

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Arctucas, do you see any difference in the CPU tests?

my cpuphotoworxx, zlib and aes results have increased as well

I see negligible differences in the CPU test, probably normal variation.

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Fiery, do you have a Intel contact you should talk to about this?, similar behavior is found on Sandy and Ivy Bridge, but not Sandy Bridge E.

Yes, we do. We'll contact them, but first we have to perform quite a few test runs to make sure we can provide exact numbers ("hard facts") in both states, on Sandy Bridge + Ivy Bridge + Sandy Bridge-E systems as well. It will take some time to gather that data, and we'll only be able to start that test session after the next AIDA64 stable update is released (which should be out in less than 2 weeks). So please provide us a bit more time to gather *.* before we can contact Intel ;)

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I think we've figured out what the reason behind the C-State anomaly. Apparently Intel Turbo Boost only considers a core sleeping (inactive) when it enters either the C3 or C6 state:

http://download.inte...nots/320354.pdf

(Check 3.3 and 3.4 in the PDF)

Hence, if you disable C-States (C3 and C6), Turbo Boost will work less efficiently. And that effectively means that single-threaded performance will suffer when you disable C-States. It is reflected by AIDA64 memory benchmarks which are single-threaded benchmarks. It will not be reflected by multi-threaded benchmarks like AIDA64 CPU and FPU benchmarks -- or Sandra memory benchmarks for that matter.

BTW, if you check the measured core clock on the Cache & Memory Benchmark Panel, you may see that with C-States enabled your processor will work at a higher core clock level. On our test system (Core i7-2600 + Gigabyte Z68XP-UD3-iSSD) Turbo Boost could push the CPU up to 3.70 GHz during the memory benchmarks when C-States were enabled, but it managed to push the CPU up to only 3.50 GHz with C-States disabled.

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It is true that the single core turbo multiplier requires C state tech, but in my case, its not related

When a user sets a multiplier under the stock multiplier, the cpu will always run at that multiplier. I found my asus bios tended to jump to 22x single core turbo at times even when i had turbo boost off and the cpu set to 20x, and 4Ghz was needing to much voltage.

in my case, my clock rate is attained from 200x19x. 20x is the normal multiplier for this processor, with turbo being 21x(all cores) and 22x(single core). My CPU is always at 3800mhz regardless of c-state tech (with high performance profile set) so the turbo ratio is not applicable here

I have heard another theory about this which sounds more likely.

Nahalem was designed with a quad channel partition in mind, but the consumer level parts are Tri channel only. When the cpu is completely awake, 2 of the cores fight over dram latching and result in a slightly reduced throughput.

When the cores are able to enter the c state, only the currently active cores attempt to latch and higher throughput is obtained.

This doesn't explain why SBE throughput is not improved with C State tech however.

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