alxns

I've been doing too much RAM testing lately... Thanks for the quick fix! It works now.

Hello, I'm not sure whether this is a bug... The activate to activate delay timings (tRRD) seem to be wrong in the north bridge (IMC) info page. So here I have tRRDL (same bank group) 9T and tRRDS (different bank group) 18T, although BIOS and other software will show what I set, i.e. tRRDL 6T and tRRDS 4T. Not sure why there is also a "different rank" reading for RAS to RAS delay What should I trust? Thanks!

Ah yes I see what you mean. Looking at VDD power and Package power for instance, there is some discrepancy. So only CPU Package power should be accurate. AIDA is a little behind for Ryzen! For example, DRAM:FSB should really be replaced by FCLK:UCLK:MEMCLK ratios (fabric, IMC and memory clocks). AFAIK, AIDA does not even show FCLK..? Anyway, I'll make sure to update to the latest beta versions. Thanks Fiery!

Hi Fiery, thanks for the support. I just want to confirm that on my system, it is only the voltages that are incorrect, interestingly. If you look at the dump file I attached, currents and powers are correct (values effectively higher for VDD than for VDDNB, as it should be)

Hello, As title suggests, VDD voltage (SVI2 TFN core sensor) and VDDNB voltage (SVI2 TFN SoC sensor) are inverted on my system. Powers and currents are correct. MB: MSI B450M Pro-M2 MAX CPU: Ryzen 5 3600 Sensors page report attached. Thanks! sensors.htm