Memory Latency

[andregrimm]

Hi there!

I'm trying to find out how the measured memory latency can be associated to the timing information.

I've got a DDR3-SDRAM with 9-9-9-24 timing at 666 MHz. My measured latancy is about 71 ns.

Could anyone please explain how this correlates?

Thanks

André

[Fiery]

666 MHz means your memory cycle time is 1.5 ns, which equals to 1T. The memory chips are made of a matrix of cells, where there are a certain number of columns and rows. The 4 timing values represent the time your memory chips will take to access a row, a column, and then finally the actual data. The first 9 means CAS Latency = 9T = 9 x 1.5 ns in your case. The second 9 is for RCD, the third 9 is for RP, and the 24 is for RAS. It's quite a complex method, but you can read more about it at:

http://en.wikipedia.org/wiki/Memory_timings

Regards,

Fiery

[andregrimm]

Thanks for your answer.

But, I know about the timings. It just that I'm not able to find any correlation to my measured value 71ns.

At first I think the real frequency the memory is working with is 166MHz. 666MHz is only from prefetching data.

But also using this value (1/166 = 6ns) could not explain where this 71ns come from.

So here some more details what I'd like to do:

I measured the memory latency and now, I want to find out, if that value is what to expect by using the manufacture informations.

Is this even possible?

Best regards

André Grimm

[Fiery]

Since there're several other factors (like memory controller's own latency), it's not possible to directly translate clocks+CL/RCD/RP/RAS timings into memory latency. Please note that clocks and CL/RCD/RP/RAS latency values are detected, while memory latency is measured.

[andregrimm]

OK, thank you again.

So one can say:

71ns memory latency, that is 1/166MHz = 6ns/T -> 71ns/6ns = 11,8T

So 11,8-9 -> 2,8T some other delays?

[Fiery]

There's no clear formula, especially since there are command delays, data throughput, data latency and a lot of other factors involved.