MAA 1 Report post Posted May 3 Hello, Please add info about bus width and clock for each cache L1/L2/L3/L4, and info about type (exclusive, inclusive). Quote Share this post Link to post Share on other sites
Fiery 416 Report post Posted May 14 On 5/3/2020 at 8:59 PM, MAA said: Hello, Please add info about bus width and clock for each cache L1/L2/L3/L4, and info about type (exclusive, inclusive). Thank you for your suggestion. We currently cannot promise anything about future feature additions. Quote Share this post Link to post Share on other sites
