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MAA

Info about caches

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Hello,

Please add info about bus width and clock for each cache L1/L2/L3/L4, and info about type (exclusive, inclusive).

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On 5/3/2020 at 8:59 PM, MAA said:

Hello,

Please add info about bus width and clock for each cache L1/L2/L3/L4, and info about type (exclusive, inclusive).

Thank you for your suggestion.  We currently cannot promise anything about future feature additions.

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