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MrX1980

DEVSLP support ?

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Hello, I'm missing the value "DEVSLP" (device sleep) in Storage -> ATA -> ATA Device Features or SSD Features

 

http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/serial-ata-ahci-tech-proposal-rev1_3_1.pdf

http://www.sata-io.org/documents/SATA-DevSleep-and-RTD3-WP.pdf

 

Should be visible like this (if possible):

Device Sleep (DEVSLP) = Supported, Enabled

 

Thanks

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Thank you, but we haven't found the actual method to detect the Device Sleep capability and status in any of the documents we've got.  It is possible via the IDENTIFY DEVICE command, but even the latest ACS doc doesn't mention Device Sleep, DEVSLP or DevSleep.  So we don't know which register to use.

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Hi, what about this ?

 

serial-ata-ahci-tech-proposal-rev1_3_1.pdf

page 9ff

 

Offset 44h: PxDEVSLP – Port x Device Sleep

bit = 1

 

Device Sleep Present (DSP):
If set to „1", the platform supports Device Sleep on this port.
If cleared to „0‟, the platform does not support Device Sleep on this port.

 

Else can you try to contact james.a.boyd@intel.com ?

My experience is not enough to ask the right questions :-)

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What we need is those feature bits to appear in the ATA/ATAPI Command Set specifications.  But as it seems, it's not been propagated for ACS-3 (latest revision), so I guess we would need to wait for ACS-4 to be drafted.

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What we need is those feature bits to appear in the ATA/ATAPI Command Set specifications.  But as it seems, it's not been propagated for ACS-3 (latest revision), so I guess we would need to wait for ACS-4 to be drafted.

 

As this actually is my area of expertise, that is exactly correct.  While it can be supported and some iteration implemented, it is still in proposal and pre-draft stages.  :D

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As this actually is my area of expertise, that is exactly correct.  While it can be supported and some iteration implemented, it is still in proposal and pre-draft stages.  :D

 

I'm glad you chimed in :) If it doesn't violate any protocols or NDAs, would you please share the pre-draft register locations and bit fields -- where the DevSleep capability and status can be detected -- with us?  Or shall we wait for the first public ACS-4 drafts to become available for download?

 

Thanks,

Fiery

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Now supported with Version: 3.20.2651 (Nov 06, 2013)

 

  • Storage / ATA / Automatic Partial to Slumber Transitions detection
  • Storage / ATA / Device Initiated Interface Power Management detection
  • Storage / ATA / DEVSLP detection
  • Storage / ATA / Hardware Feature Control detection
  • Storage / ATA / Host Initiated Interface Power Management detection
  • Storage / ATA / HPA Security Extensions detection
  • Storage / ATA / Hybrid Information Feature detection
  • Storage / ATA / IDLE IMMEDIATE With UNLOAD FEATURE detection
  • Storage / ATA / Link Power State Device Sleep detection
  • Storage / ATA / NCQ Autosense detection
  • Storage / ATA / NCQ Streaming detection
  • Storage / ATA / Service Interrupt detection
  • Storage / ATA / various ATA commands detection
  • Storage / SMART / special support for OCZ Vector 150 SSDs
  • ...

 

Thanks

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